יוסי בן-אשר - הפקולטה למדעי המחשב והמידע

פרסומים▼

cpuC: A Dynamic Reconfigurable Architecture for CNNs Acceleration, Ben-Asher, Y., Danial, J., Qashqoush, I., Gilgor, R. & Stein, E., 2025, Proceedings - 2025 IEEE 18th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2025. Institute of Electrical and Electronics Engineers Inc., p. 710-717 8 p. (Proceedings - 2025 IEEE 18th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2025).
Overcoming Core Challenges in Monocular Camera Drone Navigation of Unknown Maze, Danial, J. & Asher, Y. B., 2025, 2025 11th International Conference on Mechatronics and Robotics Engineering, ICMRE 2025. Institute of Electrical and Electronics Engineers Inc., p. 13-19 7 p. (2025 11th International Conference on Mechatronics and Robotics Engineering, ICMRE 2025).
An Extended pipeline RISC-V CPU architecture, Ben-Asher, Y. & Qashqoush, I., 2024, Proceedings - 2024 IEEE 17th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2024. Institute of Electrical and Electronics Engineers Inc., p. 517-523 7 p. (Proceedings - 2024 IEEE 17th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2024).
OCA - Code Advisory Tool for OpenMP Parallelization of Sequential Code, Haber, G., Altman, S., Ben-Asher, Y. & Aguston, C., 2023, Proceedings - 2023 16th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2023. Institute of Electrical and Electronics Engineers Inc., p. 89-96 8 p. (Proceedings - 2023 16th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2023).
Using Multiple Clocks in Highlevel Synthesis to overcome unbalanced clock cycles, Asher, Y. B. & Qashqoush, I., 2023, Proceedings - 2023 16th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2023. Institute of Electrical and Electronics Engineers Inc., p. 552-559 8 p. (Proceedings - 2023 16th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2023).
Light Monocular Camera-based Obstacle Detection and Avoidance Algorithm for Small drone Flying in an unknown Maze, Danial, J. & Asher, Y. B., 2023, Europe ISR 2023 - International Symposium on Robotics, Proceedings. VDE Verlag GmbH, p. 189-196 8 p. (Europe ISR 2023 - International Symposium on Robotics, Proceedings).
ZigZag Algorithm: Scanning an Unknown Maze by an Autonomous Drone, Danial, J. & Asher, Y. B., 2022, Proceedings - 2022 6th IEEE International Conference on Robotic Computing, IRC 2022. Institute of Electrical and Electronics Engineers Inc., p. 421-424 4 p. (Proceedings - 2022 6th IEEE International Conference on Robotic Computing, IRC 2022).
Resolving battery status and customer matching to create 24/7 drones based advertisement system, Danial, J., Ben Asher, Y. & Feldman, D., 2021, Proceedings - 2021 5th IEEE International Conference on Robotic Computing, IRC 2021. Institute of Electrical and Electronics Engineers Inc., p. 131-136 6 p. (Proceedings - 2021 5th IEEE International Conference on Robotic Computing, IRC 2021).
An Algorithm for Herding Cows by a Swarm of Quadcopters, Ben-Asher, Y. & Danial, J., 2021.
Unifying wire and time scheduling for highlevel synthesis, Ben Asher, Y. & Lipov, I., 16 Nov 2018, Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018. Institute of Electrical and Electronics Engineers Inc., p. 28-35 8 p. 8540210. (Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018).
An FPGA scalable parallel viterbi decoder, Ben Asher, Y., Tartakovsky, V., Portman, K., Zilberman, O. & Hadar, A., 16 Nov 2018, Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018. Institute of Electrical and Electronics Engineers Inc., p. 8-15 8 p. 8540207. (Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018).
A study of conflicting pairs of compiler optimizations, Asher, Y. B., Haber, G. & Stein, E., 2 Jul 2017, Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017. Institute of Electrical and Electronics Engineers Inc., p. 52-58 7 p. (Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017; vol. 2018-January).
Fine-grain power breakdown of modern out-of-order cores and its implications on skylake-based systems, Haj-Yihia, J., Yasin, A., Asher, Y. B. & Mendelson, A., Dec 2016, In: ACM Transactions on Architecture and Code Optimization. 13, 4, 56.
Adaptive Booth Algorithm for Three-integers Multiplication for Reconfigurable Mesh, Asher, Y. B. & Stein, E., 1 Mar 2016, In: Journal of Interconnection Networks. 16, 1, 1550009.
RM-circuits: Toward Feasible Use of Reconfigurable Mesh Algorithms, Ben-Asher, Y., Stein, E. & Tartakovsky, V., 2016, Proceedings of PDPTA 2016 - the International Conference on Parallel and Distributed Processing Techniques and Applications.
Generating ASIPs with reduced number of connections to the register-file, Asher, Y. B., Lipov, I., Tartakovsky, V. & Tiv, D., 22 Dec 2015, Proceedings - 2015 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2015. Carro, L. & Soudris, D. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 238-245 8 p. 7363681. (Proceedings - 2015 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2015).
Parallelization Hints via Code Skeletonization, Aguston, C., Asher, Y. B. & Haber, G., 1 Nov 2015, In: IEEE Transactions on Parallel and Distributed Systems. 26, 11, p. 3099-3107 9 p., 6987337.
DOEE: Dynamic optimization framework for better energy efficiency, Haj-Yihia, J., Yasin, A. & Ben-Asher, Y., 2015, In: Simulation Series. 47, 4, p. 107-114 8 p.
A study of manycore shared memory architecture as a way to build SOC applications, Asher, Y. B., Shajrawi, Y., Gendel, Y., Haber, G. & Segal, O., 2015, In: Simulation Series. 47, 4, p. 174-181 8 p.
Compiler-directed power management for superscalars, Haj-Yihia, J., Asher, Y. B., Rotem, E., Yasin, A. & Ginosar, R., 1 Dec 2014, In: ACM Transactions on Architecture and Code Optimization. 11, 4, 48.
Adaptive booth algorithm for three-integers multiplication for reconfigurable mesh, Stein, E. & Asher, Y. B., 27 Nov 2014, Proceedings - IEEE 28th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2014. IEEE Computer Society, p. 211-219 9 p. 6969390. (Proceedings - IEEE 28th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2014).
Parallelization hints via code skeletonization, Aguston, C., Asher, Y. B. & Haber, G., Aug 2014, In: ACM SIGPLAN Notices. 49, 8, p. 373-374 2 p.
Using Multi-op instructions as a way to generate ASIPs with optimized pipeline structure, Asher, Y. B., Lipov, I., Tartakovsky, V. & Tiv, D., 21 Jul 2014, Proceedings - 2014 IEEE 22nd International Symposium on Field-Programmable Custom Computing Machines, FCCM 2014. Institute of Electrical and Electronics Engineers Inc., p. 29 1 p. 6861578. (Proceedings - 2014 IEEE 22nd International Symposium on Field-Programmable Custom Computing Machines, FCCM 2014).
1K manycore FPGA shared memory architecture for SOC, Ben-asher, Y., Gendel, J., Haber, G., Segal, O. & Shajrawi, Y., 26 Feb 2014, Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays. 1 p.
Parallelization hints via code skeletonization, Aguston, C., Ben Asher, Y. & Haber, G., 6 Feb 2014, PPoPP 2014 - Proceedings of the 2014 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming. Association for Computing Machinery, p. 373-374 2 p. (Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP).
Parallelization hints via code skeletonization, Aguston, C., Ben Asher, Y. & Haber, G., 6 Feb 2014, In: ACM SIGPLAN Notices. 49, 8, p. 373-374 2 p.
Optimizing wait states in the synthesis of memory references with unpredictable latencies, Ben-Asher, Y., Meldiner, R. & Rotem, N., Dec 2013, In: ACM Transactions on Reconfigurable Technology and Systems. 6, 4, 19.
Hybrid type legalization for a sparse SIMD instruction set, Asher, Y. B. & Rotem, N., Sep 2013, In: Transactions on Architecture and Code Optimization. 10, 3, p. 1-14
Using memory profile analysis for automatic synthesis of pointers code, Asher, Y. B. & Rotem, N., Mar 2013, In: Transactions on Embedded Computing Systems. 12, 3, 68.
Fast evaluation of boolean circuits based on two-players game and optical connectivity circuits, Asher, Y. B., Fisher, E., Haber, G. & Tartakovsky, V., 2012, Proceedings - 41st International Conference on Parallel Processing, ICPP 2012. p. 21-29 9 p. 6337627. (Proceedings of the International Conference on Parallel Processing).
PCA - Proactive Channel Allocation for Multi-Hop Ad-Hoc Networks, Ben-Asher, Y. & Ezra, Y., 2012.
Combining Cache Aware Scheduling with Lazy Threads, Ben-Asher, Y. & Kulish, G., 2012.
Multicore Programming Using the ParC Language, Ben-Asher, Y., 2012, Springer London. 361 p.
Combining static and dynamic array detection for binary synthesis with multiple memory ports, Rotem, N. & Asher, Y. B., Mar 2011, In: Design Automation for Embedded Systems. 15, 1, p. 1-18 18 p.
Auctions by price and distance via cellular phones, Asher, Y. B. & Saleh, M. A., Mar 2011, In: Electronic Commerce Research and Applications. 10, 2, p. 155-169 15 p.
Computing the correct Increment of Induction Pointers with application to loop unrolling, Asher, Y. B. & Haj-Yihia, J., Nov 2010, In: Journal of Systems Architecture. 56, 12, p. 654-666 13 p.
Finding the best compromise in compiling compound loops to Verilog, Ben-Asher, Y., Rotem, N. & Shochat, E., Sep 2010, In: Journal of Systems Architecture. 56, 9, p. 474-486 13 p.
HparC: A mixed nested shared memory and message passing programming style intended for grid, Asher, Y. B., Giver, D., Haber, G. & Kulish, G., 2010, Proceedings of SYSTOR 2010 - The 3rd Annual Haifa Experimental Systems Conference. 13. (ACM International Conference Proceeding Series).
Automatic memory partitioning: Increasing memory parallelism via data structure partitioning, Asher, Y. B. & Rotem, N., 2010, Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'10. p. 155-161 7 p. (Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'2010).
Source level merging of independent programs, Ben Asher, Y. & Yuda, M., Jun 2009, In: Journal of Parallel and Distributed Computing. 69, 6, p. 521-531 11 p.
The effect of unrolling and inlining for python bytecode optimizations, Asher, Y. B. & Rotem, N., 2009, Proceedings of the Israeli Experimental Systems Conference, SYSTOR 2009. p. 14 1 p. (ACM International Conference Proceeding Series).
Synthesis for variable pipelined function units, Ben-Asher, Y. & Rotem, N., 2008, 2008 International Symposium on System-on-Chip Proceedings, SOC 2008. 4694874. (2008 International Symposium on System-on-Chip Proceedings, SOC 2008).
Aggressive function inlining: Preventing loop blockings in the instruction cache, Asher, Y. B., Boehm, O., Citron, D., Haber, G., Klausner, M., Levin, R. & Shajrawi, Y., 2008, In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 4917 LNCS, p. 384-397 14 p.
Extending Booth algorithm to multiplications of three numbers on FPGAs, Asher, Y. B. & Stein, E., 2008, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 333-336 4 p. 4762411. (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008).
Source level merging of independent programs, Asher, Y. B. & Yuda, M., 2007, 16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007. p. 402 1 p. 4336230. (Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT).
Ad-hoc routing using virtual coordinates based on rooted trees, Ben-Asher, Y., Feldman, M. & Feldman, S., 2006, Proceedings - Thirteenth International Symposium on Temporal Representation and Reasoning, TIME 2006. p. 6-13 8 p. 1636153. (Proceedings - IEEE International Conference on Sensor Networks, Ubiquitous, and Trustworthy Computing; vol. 2006 II).
Compact representations of search in complex domains, Ben-Asher, Y. & Farchi, E., Jun 2005, In: International Game Theory Review. 7, 2, p. 171-188 18 p.
Y-invalidate: A new protocol for implementing weak consistency in DSM systems, Ben-Asher, Y. & Podvolny, D., 2001, In: International Journal of Parallel Programming. 29, 6, p. 583-606 24 p.
Parallel solutions of indexed recurrence equations, Ben-Asher, Y. & Haber, G., 1997, In: Proceedings of the International Parallel Processing Symposium, IPPS. p. 413-417 5 p.
Bus-usage method for the analysis of reconfiguring networks algorithms, Ben-Asher, Y. & Schuster, A., 1992, Proceedings of the International Conference on Parallel Processing. Publ by IEEE, p. 146-149 4 p. (Proceedings of the International Conference on Parallel Processing).

תחומי מחקר▼

חישוב מקבילי
מערכות הפעלה
מהדרים

הפקולטה למדעי המחשב והמידע

אוניברסיטת חיפה

פרופ' יוסי בן-אשר

פרסומים▼

תחומי מחקר▼